- The gem5 simulator is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture.
- 2012-11-12 - The schedule for our user workshop at MICRO-45 is available here.
- 2012-05-30 - We've posted slides and most importantly video of a tutorial at HiPEAC Computer Systems Week. See Tutorials.
- 2012-02-11 - There have been some major changes with gem5 over the last couple of weeks. The modes (SE/FS) have been removed and a single binary can now run both compiled programs and full operating systems. Additionally, the memory system is undergoing an overhaul to better define behavior between components and make interfacing with things like SystemC easier. If you run into any issues because of these changes please let us know on the mailing list.
- 2011-11-09 - Pre-compiled disk images and kernels for Android, as well as a new web-browser benchmark, BBench, are available now. Download them here: BBench-gem5 and BBench.
- 2011-06-03 - We just finished a tutorial at ISCA 2011. The slides of the tutorial are available here. We will post a podcast of the tutorial soon assuming the recording works.
- 2011-05-01 - We're holding a tutorial at "ISCA 2011". Please join us in San Jose on Sunday June 5th, 2011.
- 2011-05-01 - The M5 and GEMS simulators are in the process of merging. As part of these changes you'll see references to gem5 (pronounced gem-five), a new website, logo, mailing lists, etc in the coming months.
- The current public release of the gem5 simulator is available at http://repo.gem5.org. (See the Repository page for details.) Auxiliary files are available on on our Download page. Please look at the sidebar for links to file bugs and for mailing list subscription information.
- Pervasive object orientation. Major simulation structures (CPUs, busses, caches, etc.) are represented as objects, both externally and internally. The gem5 configuration language allows flexible composition of these objects to describe complex simulation targets, e.g., multi-system networks where each system comprises multiple CPUs and a hierarchy of caches. The simulator's internal object orientation (using C++) provides in addition to the usual software engineering advantages.
- Multiple interchangeable CPU models. The gem5 simulator currently provides three interchangeable CPU objects: a simple, functional, one-CPI CPU; a detailed model of an out-of-order SMT-capable CPU; and a random memory-system tester. The first two models use a common high-level ISA description.
- Event-driven memory system. The gem5 simulator features a detailed, event-driven memory system including non-blocking caches and split-transaction busses. These components can be arranged flexibly, e.g., to model complex multi-level cache hierarchies. The caches support a separable coherence policy module; gem5 currently includes a simple snooping cache coherence protocol.
- Multiple ISA support. The gem5 simulator decouples ISA semantics from its timing CPU models, enabling effective support of multiple ISAs. The gem5 simulator currently supports the Alpha, ARM, SPARC, MIPS, POWER and x86 ISAs. See Supported Architectures for more information.
- Full-system capability.
- Alpha: The gem5 simulator models a DEC Tsunami system in sufficient detail to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio. We have also booted HP/Compaq's Tru64 5.1 operating system in the past, though we no longer actively maintain that capability.
- ARM: The gem5 simulator can model up to four cores of a Realview ARM development board with sufficient detail to boot unmodified Linux 2.6.35+ with a simple or out-of-order CPU.
- SPARC: The gem5 simulator models a single core of a UltraSPARC T1 processor with sufficient detail to boot Solaris in a similar manner as the Sun T1 Architecture simulator tools (building the hypervisor with specific defines and using the HSMID virtual disk driver).
- x86: The gem5 simulator supports a standard PC platform
- Multiprocessor / multi-system capability. Thanks to gem5's object orientation, instantiation of multiple CPU objects within a system is trivial. Combined with the snooping bus-based coherence protocol supported by the caches, gem5 can model symmetric multiprocessor systems. Because a complete system is just a collection of objects (CPUs, caches, memory, etc.), multiple systems can be instantiated within a single simulation process. In conjunction with full-system modeling, this feature allows simulation of entire client-server networks.
- Application-only support. In application-only (non-full-system) mode, gem5 can execute a variety of architecture/OS binaries with OS emulation or SimpleScalar Alpha EIO trace files.
- Platforms. The gem5 simulator runs on most operating systems (Linux, MacOS X, Solaris, OpenBSD, Cygwin) and architectures (x86, x86-64, SPARC, Alpha, and PPC). However, all guest platforms aren't supported on all host platforms (most notably Alpha requires little-endian hardware). It is readily portable to other hosts and other Unix-like operating systems that are supported by GCC. Alpha binaries to run on gem5 (including the full Linux kernel) can be built on x86 systems using gcc-based cross-compilation tools, so no Alpha hardware is needed to make full use of M5.
- Licensing. The gem5 simulator is released under a Berkeley-style open source license. Roughly speaking, you are free to use our code however you wish, as long as you leave our copyright on it. For more details, see the LICENSE file included in the source download. Note that the portions of M5 derived from other sources are also subject to the licensing restrictions of the original sources.
There are several sources of documentation for gem5:
- The most detailed and up-to-date documentation is on this wiki. The documentation page serves as a general table of contents for these pages. There is also a list of Frequently Asked Questions.
- We have archived material from various tutorials, which provide a more organized overview than the wiki, along with some "how to" information not currently found elsewhere.
- A higher-level overview of gem5 can be found in our article The gem5 Simulator from the May 2011 issue of ACM SIGARCH Computer Architecture News. If you use gem5 in your research, we would appreciate a citation to this paper in any publications you produce.
- The gem5 code is (somewhat sparsely) commented with doxygen comments. You can browse the doxygen-generated documentation here.
A list of publications using the gem5 simulator is also available. Please append to the list if you publish a paper using gem5.
If you use gem5 in your research, we would appreciate a citation to, The gem5 Simulator, from the May 2011 issue of ACM SIGARCH Computer Architecture News in any publications you produce.
The gem5 simulator has been developed with generous support from several sources, including the National Science Foundation, AMD, ARM, Hewlett-Packard, IBM, Intel, MIPS, and Sun. Individuals working on gem5 have also been supported by fellowships from Intel, Lucent, and the Alfred P. Sloan Foundation. This material is based upon work supported by the National Science Foundation under the following grants: CCR-0105503, CCR-0219640, CCR-0324878, EAI/CNS-0205286, and CCR-0105721.
Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF) or any other sponsor.